1. Field of the Invention
The present invention relates to a semiconductor memory device and, particularly, to a high speed serial accessible dual port semiconductor memory device.
2. Description of the Prior Art
In a compact computer such as a personal computer, a dual port memory for image processing, which is to be arranged between a CPU and a data display device to write/read display data under control of the CPU is commercially available and used widely. Such dual port memory has a random access port and a serial access port such as disclosed in U.S. Pat. No. 4,633,441 issued to S. Ishimoto on Dec. 30, 1986 and assigned to NEC corporation. The serial access port of the conventional dual port memory includes a memory cell array composed of a number of memory cells arranged at respective intersections of a plurality of rows and a plurality of columns, means for selecting one of the rows in response to a row address signal, means for transferring memory information of respective memory cells connected to the selected row in synchronism with transfer control signal and a data register for temporarily storing thus transferred information. Further, in order to serially read the temporarily stored data in the data register, the serial access port includes a serial data output buffer, a serial data output terminal, data shift means for sequentially shifting data up in synchronism with a first control signal, switch means responsive to an output of the data shift means for selecting one of data read out from the data register, a read bus line for connecting, through the switch means, the output of the data register to the serial data output buffer, means for decoding a row address signal for selecting one of the plurality of rows and initial value setting means for setting an initial value of the data shift means to an output of the decode means in synchronism with the transfer control signal and operates to output the output of the data register from the serial data output buffer.
On the other hand, with the recent development of semiconductor manufacturing technique, miniaturization of circuit elements on a semiconductor chip is enhanced, so that an area of the semiconductor chip required for one bit of memory cell is reduced, resulting in an increase of memory capacity from 256 K bits several years ago through 1 M bits to recent 4 M bits.
However, as disclosed in U.S. Pat. No. 4,989,181 issued to M. Harada on Jan. 29, 1991 and assigned to NEC corporation, miniaturization of circuit elements may cause the number of defects per semiconductor chip to be increased, so that the yield of such semiconductor memory device may be lowered. In order to avoid such degradation of yield, Harada employs the redundancy circuit technology.
A redundancy circuit of a serial access port of a conventional dual-port memory described in Harada includes a counter circuit having an externally supplied address signal code word as an initial value and incrementing from it in response to a first control signal, a defective address memory circuit for storing an address of a memory cell, a bit line and/or a serial register at which a defect is contained and a coincidence detection circuit for comparing an output of the counter circuit with an output of the defective address memory circuit. The redundancy circuit operates in response to a second control signal produced by the coincidence detection circuit upon detection of a coincidence of the outputs of the counter circuit and the defective address memory circuit to substitute a redundancy memory cell, a redundancy bit line and a redundancy serial register of the redundancy circuit for the defective memory cell, the defective bit line and/or the defective serial register, respectively.
The conventional dual-port semiconductor memory including such redundancy circuit as mentioned above sets the address signal code word in the counter circuit as well as a shift register included in the dual-port memory as their initial values in a serial read mode. Then, the shift register is incremented from the initial value by the first control signal as clock signal synchronized with an external clock. At the same time, the counter circuit is incremented by the first control signal and the output of the counter circuit is compared with the output of the defective address memory circuit.
The second control signal becomes active when the comparison indicates a coincidence upon which the redundancy circuit substitutes the memory cell, the bit line and/or the data register, which contains defect, by the memory cell, the bit line and/or the data register of the redundancy circuit having a corresponding address and reads a value stored in the data register of the redundancy circuit to an output portion of the serial port of the dual port memory. On the other hand, when the comparison indicates non-coincidence, the second control signal becomes inactive and the output value of the data register which has been transferred from the main memory cell in response to the output of the shift register and stored therein is read out to the output portion of the serial port. With the operations mentioned above, a cycle of serial read operation is completed and the first control signal is shifted to a next read out cycle. By repeating this operation cycle, the output of the data register is read out sequentially to the output portion of the serial port in response to the output of the shift register.
In the dual-port memory having such conventional redundancy circuit, however, time required to read from the serial port (referred to as "serial read time") is a sum of a shift operation time for shifting the output value of the data register to the serial port in response to the shift operation of the shift register due to the first control signal and a count-up coincidence detection time from a start time of count-up operation of the counter circuit by the first control signal to a time of coincidence detection between the outputs of the counter circuit and the defective address memory circuit. It is well known that the shift operation time is shorter than the count-up coincidence detection time. That is, the serial read time of the dual-port memory having the redundancy circuit is larger, so that an image processing speed of the dual-port semiconductor memory device becomes low.
In the serial read operation of the conventional dual-port memory mentioned above, the counter circuit counts up the first control signal one by one and the content of the counter circuit is compared with the value of the address which contains defect. Therefore, the comparison is performed for addresses subsequent to the initial value corresponding to the address code word. This means that, when there is any defect at the address corresponding to the initial value, it can not be substituted by a corresponding address of the redundancy circuit. In order to avoid this problem, it is necessary to access the address on the chip corresponding to the initial value by driving the counter circuit with another control signal and, therefore, the serial read control becomes complicated correspondingly.